1. Field of the Invention
Embodiments of the present invention generally relate to integrated circuits (ICs) and more particularly to soft error resistant fuse latch circuits.
2. Description of the Related Art
When alpha particles or cosmic rays strike an integrated circuit (IC) device, ionization paths through the device may result in an accumulation of charge. If this accumulation of charge reaches a switching node, such as an input gate of a transistor, the voltage level at the switching node may change sufficiently to switch the logic level at an output node. (As used herein, the term node generally refers to any connection point to a circuit.) Such a change to an erroneous logic level due to a spontaneous occurrence is referred to as a soft error. Reducing IC geometries increase the likelihood of soft errors in dense designs such as DRAMs. For example, as IC dimensions get smaller and smaller, the electrical charges involved in switching or holding nodes at certain voltages (referred to as a critical charge) become smaller too.
Soft errors are referred to as soft because, in most cases, the errors may be easily corrected by overwriting the erroneous data with valid data. For example, in the case of memory cells, data may be overwritten frequently, so that soft errors may indeed be short lived. However, soft errors may also occur in latches. Some latches, such as fuse latches, are only set once during a power-up sequence. In other words, soft errors occurring in fuse latches may not be corrected until the chip is powered down and a new power-up sequence occurs.
Latches are typically formed by cross-coupling a pair of inverters, such that the output of a forward inverter is connected to the input of a feedback inverter, while the output of the feedback inverter is connected to the input of the forward inverter. Inverters are typically constructed from a pair of differential transistors (e.g., one p-channel transistor and one n-channel transistor). In a typical latch configuration, a diffusion area of at least one transistor of one inverter (i.e., the output) is connected to a gate of at least one transistor of the other inverter (i.e., the input) via a metal wire. Alpha particles or cosmic ray strikes near the diffusion area of the one inverter may lead to an accumulation of positive or negative charges, which may be carried to the gate of the other inverter via the low resistance path of the metal wire. If sufficient charge is accumulated, the voltage state of the gate may be altered sufficiently to change the latched data (e.g., accumulated negative charge may reduce a high voltage level below a low logic switching threshold), resulting in a soft error. As an example, the critical charge required to flip a latch may be less than 100 fC., while alpha particle strikes may inject charges of 15 fC. to 150 fC.
Some conventional techniques for reducing soft errors in latches focus on increasing the size of the transistors used in constructing the latches. The increased transistor size may result in an increased critical charge required for causing a soft error, which may reduce the probability of soft error occurrence. However, the increased transistor sizes may also occupy more area, which runs counter to the desire to increase circuit density. Other techniques may add charge buffers in an effort to add parasitic capacitance to increase the critical charge required to cause a soft error. However, with shrinking technologies, the dimensions of the charge buffers also shrink, which may reduce their parasitic capacitance and, therefore, their effectiveness.
Accordingly, what is needed is an improved fuse latch circuit with an increased resistance to soft errors.
The present invention generally provides latch circuits having an increased resistance to soft errors.
For one embodiment, a soft error resistant latch circuit, generally includes first and second inverters, each formed of at least two transistors. At least one delay element decouples a diffusion area of at least one of the transistors of the first inverter from a gate of at least one of the transistors of the second inverter.
For another embodiment, a fuse latch having a first node and a second node generally includes a forward inverter having an input node for receiving a signal applied to the first node of the fuse latch and an output node for generating a signal on the second node of the fuse latch, a feedback inverter having an input node for receiving the signal generated by the forward inverter and an output node for generating a feedback signal. A first delay element decouples the output node of the forward inverter from the input node of the feedback inverter and a second delay element decouples the output node of the feedback inverter from the input node of the forward inverter.
For still another embodiment, a dynamic random access memory (DRAM) device generally includes a plurality of fuses and a plurality of fuse latches to store information about the state of the fuses. Each fuse latch generally includes a forward inverter having an input node for-receiving a signal indicative of the state of one of the fuses, a feedback inverter having an input node for receiving a signal generated by the forward inverter, a first delay element to decouple an output node of the forward inverter from the input node of the feedback inverter, and a second delay element to decouple an output node of the feedback inverter from the input node of the forward inverter.